1. Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device suitable for forming dual gate electrodes with a multi layer resist process.
2. Discussion of the Related Art
As dimensions of integrated circuit devices are reduced, step coverage of a semiconductor device causes many limitations in forming patterns on a substrate. When a highly integrated semiconductor device has a step coverage in a photo etching process using only single layer resist with electron beam lithography, resistance against dry etch is reduced and resolution is lowered due to a scattering effect caused by reflection off a substrate. Accordingly, devices that could be manufactured using a single layer resist process in the past now require a photo etching process using a multi layer resist to achieve a desired resolution.
On the other hand, a multi layer resist process (MLR) has been developed using a bilayer resist or a triple layer resist. Such an MLR process is disclosed in U.S. Pat. Nos. 5,169,494, 4,826,943, and 4,891,303.
A conventional method for fabricating a semiconductor device will now be described with reference to FIGS. 1A to 1E showing cross-sectional views of process steps of the conventional method.
A gate insulating film 12 is formed on a surface of a semiconductor substrate 11, as shown in FIG. 1A, and a polysilicon layer 13 (for gate electrode formation) is formed over the gate insulating film 12. The polysilicon layer 13 is formed of a undoped amorphous polysilicon. A first photoresist film 14 is coated onto the polysilicon layer 13, and is patterned by an exposure and development process.
Next, with the first photoresist film 14 serving as a mask, n-type impurity ions are implanted into the polysilicon layer 13, as shown in FIG. 1B.
Thereafter, as shown in FIG. 1C, remaining portions of the first photoresist film 14 are removed. A second photoresist film 15 is coated onto the polysilicon layer 13, and is patterned with an exposure and development process. With the second photoresist film 15 serving as a mask, p-type impurity ions are implanted into the polysilicon layer 13.
As shown in FIG. 1D, what remains of the second photoresist film 15 is removed. The polysilicon layer 13 is annealed at a high temperature to activate and diffuse the n-type and p-type dopants. A third photoresist film 16 is coated onto the polysilicon layer 13, and is patterned using an exposure and development process.
Finally, as shown in FIG. 1E, with the third photoresist pattern 16 serving as a mask, the polysilicon layer 13 is selectively removed, forming a first gate electrode 17 with implanted n-type impurity ions, and a second gate electrode 18 with implanted p-type impurity ions. Since the polysilicon layer 13 has different etch rates in different regions, a portion of the polysilicon layer 13 where n-type impurity ions are implanted forms a first gate electrode 17 having a concave shape and a portion of the polysilicon layer 13 where p-type impurity ions are implanted forms a second gate electrode 18 having a convex shape. That is, the first and second gate electrodes 17 and 18 are formed having different shapes, which is not desirable. Thus, it is difficult to obtain the critical dimensions of the gate electrodes 17 and 18, and the characteristics of two devices are not uniform.